1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a field effect transistor to be fabricated on a silicon-on-insulator (SOI) substrate and a method of fabricating the same.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a conventional semiconductor device suggested in Japanese Unexamined Patent Publication No. 4-34980 (A).
The illustrated semiconductor device is designed to have so-called SOI structure, namely, a silicon layer 103 formed on an electrically insulating layer 102. Specifically, the illustrated semiconductor device includes a silicon substrate 101, an electrically insulating layer 102 formed on the silicon substrate 101, a silicon layer 103 formed on the electrically insulating layer 102, a gate insulating film 104 formed on the silicon layer 103, a gate electrode 105 formed on the gate insulating film 104, a source region 109 formed in the silicon layer 103 around the gate insulating film 104, a drain region 110 formed in the silicon layer 103 around the gate insulating film 104. The gate insulating film 104, the gate electrode 105, the source region 109, the drain region 110, and a channel region formed below the gate insulating film 104 between the source and drain regions 109 and 110 in the silicon layer 103 define a transistor.
A field oxide film 106 is formed on the silicon layer 103 around the transistor.
An interlayer insulating film 112 is formed covering the field oxide film 106 and the gate electrode 105 therewith. Contact holes 113 are formed throughout the interlayer insulating film 112 so as to reach the source and drain regions 109 and 110. Wiring layers 114 are formed to fill the contact holes 113 therewith.
A well region 111 is formed in the silicon layer 103 below the field oxide film 106. The well region 111 contains impurity having the same electrical conductivity as that of impurity implanted into the channel region 108.
The field oxide film 106 is partially removed to form an opening as a body contact 107. A wiring layer 115 is formed in the body contact 107 to electrically connect to the well region 111. Excessive carriers generated in a channel of the transistor are exhausted through the well region 111 and the body contact 107.
FIG. 2 is a cross-sectional view of a conventional semiconductor device suggested in “Body-Contacted SOI MOSFET Structure with Fully Bulk CMOS Compatible Layout and Process”, IEEE Electron Device Letters, Vol. 18, No. 3, March 1997, pp. 102-104.
A transistor is defined by a gate insulating film 126, a gate electrode 125, a source region 124, a drain region 123, and an SOI substrate comprised of a silicon substrate 130, an electrically insulating film 121 formed on the silicon substrate 130, and a silicon layer 122 formed on the electrically insulating film 121.
Around the transistor is formed LOCOS (Local Oxidation of Silicon) region 129 by thermally oxidizing the silicon layer 122. A thin silicon layer remains not oxidized below the LOCOS region 129, and defines a carrier path 127. The carrier path 127 makes electrical contact with a body contact region 128. Excessive carriers generated in a channel of the transistor are exhausted through the carrier path 127 and the body contact region 128.
A semiconductor device having a structure similar to the structure of the above-mentioned semiconductor device is disclosed in “Suppression of the SOI Floating-body Effects by Linked-body Device Structure”, 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 92-93.
FIG. 3 is a cross-sectional view of a conventional semiconductor device suggested in “Impact of 0.18 μm SOI CMOS Technology using Hybrid Trench Isolation with High Resistivity Substrate on Embedded RF/Analog Applications”, 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 154-155.
A transistor is defined by a gate insulating film 126, a gate electrode 125, a source region 124, a drain region 123, and an SOI substrate comprised of a silicon substrate 130, an electrically insulating film 121 formed on the silicon substrate 130, and a silicon layer 122 formed on the electrically insulating film 121.
Around the transistor, there are formed trenches 131, 132 by trench isolation process for isolating a device from others. The trench 131 does not reach the electrically insulating film 121, and hence, a portion of the silicon layer 122 remains not removed. Such a portion of the silicon layer 122 defines a carrier path 127. The carrier path 127 makes electrical contact with a body contact region 128. Excessive carriers generated in a channel of the transistor are exhausted through the carrier path 127 and the body contact region 128.
In a fully depleted SOI-MOSFET which is required to include a thin SOI layer having a thickness of 10 nm, for instance, since the well region 111 acting as a carrier path through which excessive carriers are exhausted outside is thin, the carrier path would have an increased resistance. It would be necessary to design the carrier path to have an impurity concentration higher than that of a channel in order to reduce a resistance of the carrier path. However, there is not known a process of implanting impurity into a carrier path at a high concentration in a self-aligning manner to a region where a device is to be fabricated.
Though the above-mentioned Japanese Unexamined Patent Publication No. 4-34980 (A) does not refer to a process of forming the field oxide film 106, it is considered that the field oxide film 106 is formed in accordance with a conventional method which has been used before LOCOS and trench isolation were put to practical use in a field effect transistor fabricated on a bulk substrate.
FIGS. 4A to 4C are cross-sectional views of a substrate, illustrating respective steps of a method of forming a field oxide film on an SOI substrate, which method would be obtained if steps generally used for fabricating a field effect transistor on a bulk substrate were applied to an SOI substrate.
As illustrated in FIG. 4A, impurity is implanted into a silicon layer 103 formed on an electrically insulating film 102 which is formed on a silicon substrate 101, by gas phase diffusion.
Then, as illustrated in FIG. 4B, an electrically insulating layer 106 is formed on the silicon layer 103 by thermal oxidation or chemical vapor deposition (CVD).
Then, as illustrated in FIG. 4C, the electrically insulating layer 106 is patterned by wet etching.
A transistor is fabricated in a region in which the electrically insulating layer 106 was removed. A portion of the silicon layer 103 located below the electrically insulating layer 106 acts as a carrier path.
However, the method having been explained with reference to FIGS. 4A to 4C is accompanied with a problem that it would not be possible to implant impurity having a concentration higher than that of a channel, into the carrier path. Thus, the method is not suitable to a fully depleted SOI-MOSFET which is required to include a carrier path having a high impurity concentration for reducing a parasitic resistance in the carrier path.
Though not disclosed in any documents, such a method as mentioned below may be carried out for accomplishing a carrier path having a high impurity concentration.
First, as illustrated in FIG. 5A, impurity is implanted into carrier path formed in the silicon layer 103, through a mask 116 comprised of a photoresist film or a silicon dioxide film.
After removal of the mask 116, an electrically insulating film 106 is formed on the silicon layer 103, and then, patterned, as illustrated in FIG. 5B.
This method ensures that a carrier path has an impurity concentration higher than that of a channel.
However, the method is accompanied with a problem that it would not be possible to position both the carrier path and a region in which a transistor is to be fabricated, in a self-aligning manner, resulting in that the electrically insulating film 106 is shifted when formed, as illustrated in FIG. 5C.
In the conventional methods illustrated in FIGS. 2 and 3, when a device isolation region for electrically isolating adjacent devices from each other is patterned, specifically, when a mask for the LOCOS region 129 is formed or the silicon layer 122 is etched to form the trench 131, a region in which a transistor is to be fabricated is generally covered with a resist. It would be possible to implant impurity only into the device isolation region in a self-aligning manner, if ions are using the photoresist as a mask for implantation.
However, the methods illustrated in FIGS. 2 and 3 in which a thickness of an SOI layer in a carrier path is unavoidably smaller than a thickness of an SOI layer in a channel cannot be applied to a fully depleted SOI-MOSFET which is required to have a quite thin SOI layer, because an SOI layer is eliminated in a carrier path, or an SOI layer having a thickness insufficient as a carrier path remains.
Thus, there is a first need to a method which makes it possible to implant impurity having a concentration higher than that of a channel region into a carrier path region in a self-aligning manner to the channel region, and which can be applied to SOI-MOSFET including a thin SOI layer.
The method having been explained with reference to FIG. 1 is applicable to SOI-MOSFET including a thin SOI layer, because a carrier path is not formed thinner than a channel region unlike the methods having been explained with reference to FIGS. 2 and 3.
However, the method having been explained with reference to FIG. 1 is accompanied with a problem that when the field oxide film 106 is patterned into such a pattern as illustrated in FIG. 4C or 5C, the patterned field oxide film does not have a steep end, the patterned field oxide film is narrowed in size relative to a mask, or defects are generated in the silicon layer.
If the field oxide film 106 is wet-etched in the steps illustrated in FIG. 4C or 5C, the patterned field oxide film would not have a steep end, because the field oxide film is isotropically etched. In addition, since the field oxide film 106 is latitudinally etched because of isotropic etching, a region for forming the field oxide film 106 might be narrowed.
If the field oxide film 106 is dry-etched, the patterned field oxide film could have a steep end, and it would be possible to prevent the field oxide film 106 from narrowing. However, since the silicon layer is exposed to plasma in a dry etching step, defects would be generated at a surface of the silicon layer.
Furthermore, a selection ratio of silicon to silicon dioxide in a step for dry-etching a silicon dioxide film is smaller than the same in a step for wet-etching a silicon dioxide film. Hence, a silicon layer might be etched.
Accordingly, dry-etching cannot be applied to SOI-MOSFET required to include a silicon film having a strictly controlled thickness.
Thus, there is a second need to a method which makes it possible to accomplish a steep end in a patterned field oxide film, prevent the patterned field oxide film from narrowing and being shifted in position, prevent generation of defects at a surface of a silicon layer, and prevent a silicon layer from being etched, and which can be applied to SOI-MOSFET having a thin SOI layer.
Referring back to FIG. 1, the field oxide film 106 has an upper end located higher than a surface of the silicon layer. Accordingly, when a material of which the gate electrode 105 is composed is deposited, the deposited layer has raised and recessed portions reflecting a shape of the field oxide film 106. When a gate electrode is formed, if a material from which a gate electrode is to be formed does not have a planarized surface, a resist pattern would be deformed, and hence, a resultant gate electrode would be also deformed.
If a material from which a gate electrode is to be formed does not have a planarized lower surface, when a gate electrode is formed by reactive ion etching, the reactive ion etching to a gate electrode would finish only in a region, and resultingly, an underlying gate insulating film would appear. If the material is kept etched under such condition, the exposed gate insulating film would be etched, and the underlying silicon layer would be further etched. This results that a transistor cannot be fabricated.
Thus, there is a third need to a process for enabling a material from which a gate electrode is to be formed, to have planarized upper and lower surfaces, when the material is patterned into a gate electrode by lithography and reactive ion etching.
In the conventional transistor illustrated in FIG. 1, it would be necessary to design the well region 111 acting as a carrier path region to have a high impurity concentration, in order to reduce a resistance in a carrier path region connecting the channel region and the body contact to each other.
However, if the well region 111 would contain impurity at an excessively high concentration, an electric field generated between the source/drain regions and the well region would have a great intensity, resulting in an increase in a leakage current.
Thus, there is a fourth need to a transistor which is capable of suppressing an intensity of an electric field generated between source/drain regions and a well region, and further reducing a resistance in a carrier path with a leakage current being depressed.
Japanese Unexamined Patent Publication No. 2000-269509 (A) has suggested a semiconductor device including (a) an electrical insulator, (b) a first semiconductor layer which has a first principal plane adjacent to the electrical insulator and a second principal plane located at the opposite side of the first principal plane, and has a first electrical conductivity, (c) an electrically insulating layer formed on the second principal plane, (d) a control electrode extending in a first direction above the electrically insulating layer, and divides the first semiconductor layer into first and second regions about the electrically insulating layer in a second direction perpendicular to the first direction, (e) a second semiconductor layer formed in the first region and having a second electrical conductivity, and (f) third to fifth semiconductor layers formed in the second region across the second principal plane to the first principal plane, having a first, second and first electrical conductivity, respectively, and being exposed in the second principal plane along a side edge of the control electrode.
Japanese Unexamined Patent Publication No. 2000-332250 (A) has suggested a semiconductor device having a field effect transistor, including (a) a substrate, (b) an electrically insulating film formed on the substrate, (c) a first semiconductor layer formed on the electrically insulating film, having a channel of the transistor, and having a first electrical conductivity, (d) a gate insulating film formed on the channel, (e) a gate electrode formed on the gate insulating film, (f) source and drain regions formed in the first semiconductor layer around the gate electrode so as to make electrical contact with the channel, and having a second electrical conductivity, (g) a second semiconductor layer extending from a body which is a region other than source and drain regions in the first semiconductor layer, and having a second electrical conductivity, and (h) an electrode formed in the second semiconductor layer, containing impurity having a first electrical conductivity at a concentration greater than that of the first semiconductor layer, and making electrical contact with the source or drain region.
Japanese Unexamined Patent Publication No. 2000-252471 (A) has suggested a semiconductor device including a semiconductor substrate, an electrically insulating film formed on the semiconductor substrate, a semiconductor layer formed on the electrically insulating film, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film. The semiconductor layer includes a channel region below the gate electrode. The channel region contains impurity at a low concentration. The semiconductor layer further includes a carrier path region located adjacent to the channel region, and having a surface located lower than a surface of the channel region. The carrier path region makes electrical contact with a body contact.
However, the above-mentioned needs remain unsatisfied even in the above-mentioned Publications.